View PXD1005_4719213.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

freescale semiconductor product brief document number: pxd10pb rev. 1, 06/2011 contents ? freescale semiconductor, inc., 2011. all rights reserved. the pxd10 family represents a new generation of 32-bit microcontrollers based on the power architecture ? . these devices provide a cost -effective, single chip display solution for the industr ial market. an integrated tft driver with digital vi deo input ability from an external video source, signi ficant on-chip memory, and low power design methodologies provide flexibility and reliability in meeting di splay demands in rugged environments. the advanced processor core offers high performance processing optimized for low power consumption, operating at speeds as high as 64 mhz. the family itself is fully scalable from 512 kb to 1 mb internal flash memory. the memory capacity can be further expanded via the on-chip quadspi serial flash controller module. larger me mory versions with greater graphics functionality are planned for the future. the pxd10 family platform has a single level of memory hierarchy supporting on-chip sram and flash memories. the 1 mb flash ve rsion features 160 kb of on-chip graphics sram to buffer cost effective color pxd10 product brief 32-bit power architecture ? microcontrollers for entry level display solutions 1 application examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.1 pxd10 features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.2 pxd10 block diagram. . . . . . . . . . . . . . . . . . . . . . . 4 2.3 package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2.4 module features . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 developer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4 orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
pxd10 product brief, rev. 1 application examples freescale semiconductor 2 tft displays driven via the on-chip display control unit (dcu). see table 1 for specific memory and feature sets of the product family members. the pxd10 family benefits from the extensive de velopment infrastructure for power architecture devices, which is already well established. this includes full suppor t from available software drivers, operating systems, and configuration code to assist with users? implementations. see section 3, developer support, for more information. 1 application examples the pxd10 family?s integrated displa y and motor control capability makes it suitable for applications such as: ? factory display units ? building control display units ? ruggedized displays ? industrial instrumentation ? multi-stepper motor control 2features this section describes the features of the pxd10 family. 2.1 pxd10 features table 1 displays the pxd10 feature set. table 1. pxd10 family feature set feature PXD1005 pxd1010 cpu e200z0h execution speed static ? 64 mhz flash (ecc) 512 kb 1 mb eeprom emulation block (ecc) 4 16 kb ram (ecc) 48 kb graphics ram no 160 kb mpu 12 entry edma 16 channels display control unit (dcu) no yes parallel data interface no yes stepper motor controller (smc) 6 motors
features pxd10 product brief, rev. 1 freescale semiconductor 3 stepper stall detect (ssd) yes sound generation logic (sgl) yes lcd driver 64 6 40 4, 38 6 32 khz slow external crystal oscillator yes real-time counter and autonomous periodic interrupt ye s periodic interrupt timer (pit) 4 ch, 32-bit software watchdog timer (swt) yes system timer module (stm) 4 ch, 32-bit timed i/o (emios) 8 ch, 16-bit ic/oc 16 ch, 16-bit pwm/ic/oc adc 16 channels, 10-bit can (64 mailboxes) 2 can can sampler yes sci 2 uart spi 2 spi 3 spi quadspi serial flash interface no yes i 2 c24 gpio 105 105 (144-pin package) 133 (176-pin package) debug nexus 1 nexus 2+ package 144 lqfp 144 lqfp 176 lqfp table 1. pxd10 family feature set (continued) feature PXD1005 pxd1010
pxd10 product brief, rev. 1 features freescale semiconductor 4 2.2 pxd10 block diagram figure 1 shows a top-level block diagra m of the pxd10 microcontrollers. figure 1. pxd10 block diagram crossbar switch (xbar) pxd10 block diagram integer multiply e200z0 core unit execution unit instruction unit vle general load/store unit purpose registers (32 x 32-bit) branch unit intc jtag peripheral i/o bridge (pbridge) oscillators bam rtc pll pit swt aux pll vreg stm data bus instruction bus memory protection unit (mpu) uart/lin adc lcd seg spi i 2 c emios can siu smd ssd ram controller quadspi eeprom (emulation) flash (ecc) ram controller flash controller flash (ecc) graphics sram sram (ecc) nexus2+ display control unit (tfts) edma adc ? analog-to-digital converter bam ? boot assist module can ? controller area network controller ecc ? error correction code edma ? enhanced direct memory access controller emios ? timed input/output i 2 c ? inter-integrated circuit controller intc ? interrupt controller jtag ? joint test action group interface lcd ? liquid crystal display pit ? periodic interrupt timer pll ? phase-locked loop rtc ? real time clock siu ? system integration unit smd ssd ? stepper motor driver/stepper stall detect spi ? serial peripheral interface controller sram ? static random-access memory stm ? system timer module swt ? software watchdog timer uart/lin ? universal asynchronous receiver/transmitter/ local interconnect network vle ? variable-length execution set vreg ? voltage regulator
features pxd10 product brief, rev. 1 freescale semiconductor 5 2.3 package the pxd10 microcontrollers are of fered in the following packages: ? 144 lqfp, 0.5 mm pitch, 20 mm x 20 mm outline ? 176 lqfp, 0.5 mm pitch, 24 mm x 24 mm outline 2.4 module features 2.4.1 low-power operation pxd10 devices are designed for opt imized low-power operation and dynam ic power management of the core processor and peripherals. powe r management features include so ftware-controlled clock gating of peripherals and multiple power domains to minimize leakage in low-power modes. there are two static low-power modes, standby and stop, and two dynamic power modes?run and halt. both low power modes use clock gating to halt the clock for all or part of the device. the standby mode also uses power gatin g to automatically turn off the pow er supply to parts of the device to minimize leakage. standby mode turns off the power to the majority of the chip to offer the lowest power consumption mode. the contents of the cores, on-chip peripheral re gisters and potentially some of the volatile memory are lost. standby mode is configurable to make cert ain features available with the disadvantage that these consume additional current: ? it is possible to retain the contents of the full ram or only 8 kb. ? it is possible to enable the internal 16 mhz or 128 khz rc oscillator, the external 4?16 mhz oscillator, or the external 32 khz oscillator. ? it is possible to keep the lcd module active. the device can be awakened from standby mode via from any of up to 19 i/o pins, a reset or from a periodic wake-up using a low power oscillator. stop mode maintains power to the entire device al lowing the retention of al l on-chip registers and memory, and providing a faster rec overy low power mode than the lo west standby mode. there is no need to reconfigure the de vice before executing code. the clocks to the core and peripherals are halted and can be optionally stopped to the oscillator or pll at the expense of a slower start-up time. stop is entered from run mode onl y. wake-up from stop mode is tr iggered by an external event or by the internal periodic wake-up, if enabled. run modes are the main operating mode where the enti re device can be powered and clocked and from which most processing activity is done. four dynamic run modes are s upported?run0 - run3. the ability to configure and se lect different run modes en ables different clocks and power configurations to be supported with respect to each other and to allow switching between different operating conditions. the
pxd10 product brief, rev. 1 features freescale semiconductor 6 necessary peripherals, clock sources , clock speed and system clock prescalers can be independently configured for each of the f our run modes of the device. halt mode is a reduced activity, low power mode intended for modera te periods of lower processing activity. in this mode the core sy stem clocks are stopped but user-selec ted peripheral tasks can continue to run. it can be configured to provi de more efficient power management features (switch-off pll, flash memory, main regulator, etc.) at the cost of longer wake up latency. the system returns to run mode as soon as an event or interrupt is pending.
features pxd10 product brief, rev. 1 freescale confidential proprietary, nda required freescale semiconductor 7 table 2 summarizes the operating modes of pxd10 devices. table 2. operating mode summary 1 notes: 1 table key: on?powered and clocked op?optionally configurable to be enabled or disabled (clock gated) cg?clock gated, powered but clock stopped off?powered off and clock gated fp?vreg full performance mode lp?vreg low power mode, reduced output capab ility of vreg but lower power consumption var?variable duration, based on the required reconfiguration and execution clock speed bam?boot assist module software and hardware used for device start-up and configuration operating modes soc features clock sources periodic wake-up wake-up input vreg mode wake-up time 2 2 a high level summary of some key durations that need to be cons idered when recovering from low power modes. this does not accou nt for all durations at wake up. other delays will be necessary to consider including, but not limited to the external supply start-up tim e. irc wake-up time must not be added to the overall wa ke-up time as it starts in parallel with the vreg. all other wake-up times must be added to determine the total start-up time core peripherals flash ram graphics ram main pll auxiliary pll 16 mhz irc x osc 128 khz irc 32 khz x osc vreg start-up irc wake-up flash recovery osc stabilization pll lock s/w reconfig mode switch over run onopopononopoponoponop ? ? fp ? ? ? ? ? ? ? halt cg op op on on op op on op on op op op fp ? ? ? ? ? ? tbd stop cg cg cg on on cg cg op op on op op op lp 50 s 4 s 20 s 1ms 200 s ? 24 s standby off off 3 3 the lcd can optionally be kept running while the device is in standby mode. off cg 4 4 all of the ram contents is retained , but not accessible in standby mode. off off off op op on op op op lp 50 s 8 s 100 s 1ms 200 s var 28 s off off off 8k 5 5 8 kb of the ram contents is retained, but not accessible in standby mode. off off off op op on op op op lp 50 s 8 s 100 s 1ms 200 s var 28 s por 500 s 8 s 100 s 1ms 200 s bam
pxd10 product brief, rev. 1 features freescale semiconductor 8 additional notes on low power operation: ? fast wake-up using the on-chip 16 mhz internal rc oscillator allows rapid execution from ram on exit from low power modes ? the 16 mhz internal rc oscillat or supports low speed code execut ion and clocking of peripherals when it is selected as the system clock and can also be used as the pll input clock source to provide fast start-up without th e external oscillator delay ? pxd10 devices include an intern al voltage regulator that includes the following features: ? regulates input to genera te all internal supplies ? manages power gating ? low power regulators support operation when in stop and standby modes to minimize power consumption ? startup on-chip regulators in <50 s for rapid exit of stop and standby modes ? low voltage detection on main supply and 1.2 v regulated supplies 2.4.2 e200z0h core processor the e200z0h processor is similar to other processors in the e200zx series but supports only the vle instruction set and does not include the signal processing extension for ds p applications or a floating point unit. the e200z0h has all the feat ures of the e200z0 plus: ? branch acceleration using br anch target buffer (btb) ? supports independent instruction and data accesse s to different memory subsystems, such as sram and flash memory via indepe ndent instruction and data bius the e200z0h processor uses a four stage in-order pipe line for instruction execution. the instruction fetch (stage 1), instruction decode/regis ter file read/effective address calculation (s tage 2), execute/memory access (stage 3), and regist er writeback (stage 4) stages operate in an overlapped fashion, allowing single clock instruction execution for most instructions. the integer execution unit consists of a 32-bit arithmet ic unit (au), a logic unit (lu), a 32-bit barrel shifter (shifter), a mask-inserti on unit (miu), a condition regist er manipulation unit (cru), a count-leading-zeros unit (clz), an 8 32 hardware multip lier array, result feed-forward hardware, and a hardware divider. most arithmetic and logical operations are executed in a single cycl e with the exception of the divide and multiply instructions. a count-lead ing-zeros unit operates in a single clock cycle. the instruction unit contains a pc incrementer and a dedicated branch a ddress adder to minimize delays during change of flow operations. branch target prefet ching from the btb is performed to accelerate certain taken branches. sequential prefetching is performed to ensure a supply of instructions into the execution pipeline. branch target prefetching is performed to accelerate taken branches. prefetched instructions are placed into an instruction buffer capable of holding four instructions.
features pxd10 product brief, rev. 1 freescale semiconductor 9 conditional branches not taken execute in a single clock. branches with su ccessful target prefetching have an effective execution time of one clock on e200z0h. all other taken branch es have an execution time of two clocks. memory load and store operations are provided for byte, halfword, and word (32-bi t) data with automatic zero or sign extension of byte and halfword load da ta as well as optional byte reversal of data. these instructions can be pipelined to allow effective single cycle throughput. load and store multiple word instructions allow low overhead context save and restore operations. the load /store unit contains a dedicated effective address adder to allow effective addres s generation to be optimi zed. also, a load-to-use dependency does not incur any pipeline bubbles for most cases. the condition register unit supports the condition regi ster (cr) and condition re gister operations defined by the power architecture. the condition register consists of eight 4-bit fi elds that reflect the results of certain operations, such as move, integer and floati ng-point compare, arithmetic , and logical instructions, and provide a mechanism fo r testing and branching. vectored and autovectored interr upts are supported. hardware vectored interrupt support is provided to allow multiple interrupt sources to have unique in terrupt handlers invoked with no software overhead. the cpu includes support for variable length encoding (vle) instruction enhancements. this allows the classic powerpc instruction set to be represented by a modified instruct ion set made up fr om a mixture of 16-bit and 32-bit instructions. this re sults in a significantly smaller code size footprint without affecting performance noticeably. the cpu core is enhanced by an additional interrupt source?non mask able interrupt. this interrupt source is routed directly from package pins, via edge detection logic in the siu to the cpu, bypassing the interrupt controller completely. once the edge dete ction logic is programmed, it can not be disabled, except by reset. the non mask able interrupt is, as the name suggest s, completely un-maskable and when asserted will always result in th e immediate execution of the respective interrupt service routine. the non maskable interrupt is not guaranteed to be recoverable. the cpu core has an additional ?wait for interrupt? inst ruction that is used in conjunction with low power stop mode. when low power stop mode is selected, this instruction is executed to allow the system clock to be stopped. an external interr upt source or the system wake-up ti mer is used to re start the system clock and allow the cpu to service the interrupt. additional features include: ? load/store unit ? 1-cycle load latency ? misaligned access support ? no load-to-use pipeline bubbles ? thirty-two 32-bit genera l purpose registers (gprs) ? separate instruction bus and load/store bus harvard architecture ? reservation instructions for implem enting read-modify-write constructs ? multi-cycle divide (divw) and load multipl e (lmw) store multiple (smw) multiple class instructions, can be interrupted to pr event increases in interrupt latency ? extensive system developmen t support through nexus debug port
pxd10 product brief, rev. 1 features freescale semiconductor 10 2.4.3 display control unit (dcu) the dcu is a display controller designed to drive tft lcd displays capable of driving up to wqvga resolution screens with 16 layers and 4 planes with real time alpha-blending. the dcu generates all the necessary signals required to drive the displa y: up to 24-bit rg b data bus, pixel clock, data enable, horizont al-sync and vertical-sync. internal memory resource of the pxd10 allows to ea sily handle complex graphi cs contents (pictures, icons, languages, fonts) on a color tft panel in up to wide quarter video graphics array (wqvga) sizes. all the data fetches from inte rnal and/or external memory are pe rformed by the internal four-channel dma of the dcu providing a high speed/low latency access to the system backbone. control descriptors (cds) associated with each layer enable effective merging of different resolutions into one plane to optimize use of internal memory buffers. a layer may be constructed from graphic content of various resolutions including 1bpp, 2bpp, 4bpp, 8bpp, 16bpp, 24bpp and 24bpp+alpha. the ability of the dcu to handle input data in resolutions as low as 1bpp, 2bpp and 4bpp enables a highly efficient use of internal memory resources of the pxd10. a special tiled mode can be enabled on any of the 16 layers to repeat a pattern optimizi ng graphic memory usage. a hardware cursor can be managed independently of the layers at bl ending level increasing the efficient use of the internal dcu resources. to secure the content of all critical information to be displayed, a safety mode can be activated to check the integrity of critical data along the whole system data path from the memory to the tft pads. the dcu features the following: ? display color depth: up to 24 bpp ? generation of all rgb and control signals for tft ? four-plane blending ? maximum number of input layers: 16 (fixed priority) ? dynamic look-up table (c olor and gamma look-up) ? ?? blending range: up to 256 levels ? transparency mode ? gamma correction ? tiled mode on all the layers ? hardware cursor ? critical display content integrity m onitoring for functional safety support ? internal direct memory access (d ma) module to transfer data from internal and/or external memory.
features pxd10 product brief, rev. 1 freescale semiconductor 11 2.4.4 parallel data interface (pdi) the pdi is a digital interface used to receive external digital video or graphic content into the dcu. the pdi input is directly injected into the dcu ba ckground plane fifo. when the pdi is activated, all the dcu synchronization is extracted from the external video stream to guarant ee the synchronization of the two video sources. the pdi can be used to: ? connect a video camera output directly to the pdi ? connect a secondary display driver as slave with a minimum of extra cost ? connect a device gathering various video sources ? provide flexibility to allow the dcu to be used in slave mode (e xternal synchronization) the pdi features the following: ? supported color modes: ? 8-bit mono ? 8-bit color multiplexed ? rgb565 ? 16-bit/18-bit raw color ? supported synchronization modes: ? embedded itu-r bt.656-4 (rgb565 mode 2) ? hsync, vsync ? data enable ? direct interface with dcu background plane fifo ? synchronization generation for the dcu 2.4.5 liquid crystal display (lcd) driver the lcd driver module has two configurations allowing a maximum of 160 or 228 lcd segments: ? up to 40 frontplane drivers and 4 backplane drivers ? up to 38 frontplane drivers and 6 backplane drivers each segment is controlled and can be masked by a corresponding bit in the lcd ram. four to six multiplex modes (1/1, 1/2, 1/3, 1/4, 1/5, 1/ 6 duty), and three bias (1/1, 1/2, 1/3) methods are available. all frontplane and backplane pins can be multiplexed with other port functions. the lcd driver module fe atures the following: ? programmable frame clock generato r from different clock sources: ? system clock ? internal rc oscillator ? programmable bias vol tage level selector
pxd10 product brief, rev. 1 features freescale semiconductor 12 ? on-chip generation of all output voltage levels ? lcd voltage reference ta ken from main 5v supply ? lcd ram ? contains the data to be displayed on the lcd ? data can be read from or writte n to the display ram at any time ? end of frame interrupt ? optimizes the refresh of the data without visual artefact ? provides selectable number of frames between each interrupt ? contrast adjustment using program mable internal voltage reference ? remapping capability of 4 or 6 backplanes with frontplanes ? increase pin selection flexibility ? in low power modes, the lcd operation can be suspended under software control. the lcd can also operate in low power modes, clocked by the internal 128 khz irc or external 32 khz crystal oscillator ? selectable output current boost during transitions 2.4.6 stepper motor controller (smc) the smc module is a pwm motor controller suitable to drive loads requiring a pwm signal. the motor controller has twelve pwm cha nnels associated with two pi ns each (24 pins in total). the smc module includes the following features: ? 10/11-bit pwm counter ? 11-bit resolution with select able pwm dithering function ? left, right, or center aligned pwm ? output slew rate control ? output short circuit detection this module is suited for, but not limited to, dr iving small stepper and ai r core motors used in instrumentation applications . this module can be used for other motor control or pwm applications that match the frequency, resolution, and out put drive capabilities of the module. 2.4.7 stepper stall detector (ssd) the stepper stall detector (ssd) m odule provides a circuit to measure and integrate the induced voltage on the non-driven coil of a stepper motor using full st eps when the gauge pointer is returning to zero (rtz). the ssd module features the following: ? programmable full step state ? programmable integration polarity ? blanking (recirculation) state ? 16-bit integration accumulator register
features pxd10 product brief, rev. 1 freescale semiconductor 13 ? 16-bit modulus down counter with interrupt 2.4.8 flash memory the pxd10 microcontroller has the fo llowing flash memory features: ? up to 1 mb of burst flash memory ? typical flash memory access time: 0 wait-state for buffer hits, 2 wait-states for page buffer miss at 64 mhz ? two 4 128-bit page buffers with programmable prefetch control ? one set of page buffers can be allocated for c ode-only, fixed partitions of code and data, all available for any access ? one set of page buffers allocated to display controller unit and the edma ? 64-bit ecc with single-bit correction, double-bit detection for data integrity ? 64 kb data flash memory ? separate 4 ? 16 kb flash block for eeprom emulation with prefetch buffer and 128-bit data access port ? small block flash memory arrangement to suppor t features such as boot block, operating system block ? hardware managed flash memory wr ites, erase and verify sequence ? censorship protection scheme to prev ent flash memory content visibility ? separate dedicated 64 kb data flash memory for eeprom emulation ? four erase sectors each c ontaining 16 kb of memory ? offers read-while-write functi onality from main program space ? same data retention and program erase specification as main program flash memory array 2.4.9 static random-access memory (sram) the pxd10 microcontrollers have up to 48 kb ge neral-purpose on-chip sram with the following features: ? typical sram access time: 0 wait-s tate for reads and 32-bit writes; 1 wait-state for 8- and 16-bit writes if back to back with a read to same memory block ? 32-bit ecc with single-bit correction, double bit detection for data integrity ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory ? user transparent ecc encoding and decoding for byte, half word, and word accesses ? separate internal power domain applied to full sram block, 8 kb sram block during standby modes to retain cont ents during low power mode. 2.4.10 on-chip graphics sram the pxd10 microcontroller has 160 kb on-chip gr aphics sram with th e following features: ? usable as general purpose sram ? typical sram access tim e: 0 wait-state for r eads and 32-bit writes
pxd10 product brief, rev. 1 features freescale semiconductor 14 ? supports byte (8-bit), half word (16-bit), and wo rd (32-bit) writes for optimal use of memory 2.4.11 quadspi serial flash controller the quadspi module enables use of external seri al flash memories supporting single, dual and quad modes of operation. it features the following: ? memory mapping of external serial flash ? automatic serial flash read command generation by cpu, dma or dcu r ead access on ahb bus ? supports single, dual and quad serial flash read commands ? flexible buffering scheme to maximi ze read bandwidth of serial flash ? ?legacy? mode allowing quadspi to be used as a standard spi (no dsi or csi mode) 2.4.12 analog-to-digital converter (adc) the adc features the following: ? 10-bit a/d resolution ? 0 to 5 v common mode conversion range ? supports conversions speeds of up to 1 ? s ? 16 internal and 8 external channels support ? up to 16 single-ended inputs channels ? all channels configured to have alternat e function as general purpose input/output pins ? 10-bit 3 counts accuracy (tue) ? external multiplexer support to increase up to 23 channels ? automatic 1 8 mu ltiplexer control ? external multiplexer connected to a dedicated input channel ? shared register between the 8 external channels ? result register available fo r every non-multiplexed channel ? configurable left- or right-aligned result format ? supports for one-shot, scan and injection conversion modes ? injection mode status bit implemented on adjacent 16-bit register for each result ? supports access to result and inject ion status with single 32-bit read ? independently enabling of function for channels: ? pre-sampling ? offset error cancellation ?offset refresh ? conversion triggering support ? internal conversion triggering from periodic interrupt timer (pit) ? four configurable analog comparator channels offering range comparison with triggered alarm ? greater than
features pxd10 product brief, rev. 1 freescale semiconductor 15 ?less than ? out of range ? all unused analog inputs can be used as general purpose input and output pins ? power down mode ? optional support for dma transfer of results 2.4.13 sound generation logic (sgl) module the sgl module has two modes of operation: ? amplitude modulated pwm mode for low co st buzzers using any two emios channels ? monophonic signal with amplitude control ? 8-bit amplitude resolution ? ability to mix any two emios channels. ? requires simple external rc lowpass filter ? digital sample mode for higher quality sound using one emios channel and edma ? up to 10-bit audio amplitude resolution ? polyphonic sound synthesis ? playback of sample based waveforms ? text-to-speech possibility ? requires external lowpass filter 2.4.14 serial communication interface module (uart) the pxd10 devices include up to two uart modul es and support uart master mode, uart slave mode and uart mode. the modules are uart state machine compli ant to the uart 1.3 and 2.0 and 2.1 specifications and handle uart frame transmission and recept ion without cpu intervention. the serial communication interf ace module offers the following: ? uart features: ? full-duplex operation ? standard non return-to-zero (nrz) mark/space format ? data buffers with 4-byte receive, 4-byte transmit ? configurable word length (8-bit or 9-bit words) ? error detection and flagging ? parity, noise and framing errors ? interrupt driven operation with 4 interrupts sources ? separate transmitter and r eceiver cpu interrupt sources ? 16-bit programmable baud-rate modul us counter and 16-bit fractional ? two receiver wake-up methods ? lin features:
pxd10 product brief, rev. 1 features freescale semiconductor 16 ? autonomous lin frame handling ? message buffer to store identi fier and up to eight data bytes ? supports message length of up to 64 bytes ? detection and flagging of lin errors ? sync field; delimiter; id parity; bit, framing; checksum and timeout errors ? classic or extended checksum calculation ? configurable break duration of up to 36-bit times ? programmable baud rate prescalers (13-bit mantissa, 4-bit fractional) ? diagnostic features ? loop back ?self test ? lin bus stuck dominant detection ? interrupt driven operation with 16 interrupt sources ? lin slave mode features ? autonomous lin header handling ? autonomous lin response handling ? discarding of irrelevant lin resp onses using up to 16 id filters 2.4.15 serial peripheral interface (spi) module the spi modules provide a synchronous serial inte rface for communication betw een the pxd10 mcu and external devices. the spi features the following: ? up to two spi modules ? full duplex, synchronous transfers ? master or slave operation ? programmable master bit rates ? programmable clock polarity and phase ? end-of-transmission interrupt flag ? programmable transfer baud rate ? programmable data frames from 4 to 16 bits ? up to 6 chip select lines available, depending on package and pin multiplexing, enable 64 external devices to be selected using external muxing from a single spi ? 8 clock and transfer attributes registers ? chip select strobe available as alternate functi on on one of the chip select pins for deglitching ? fifos for buffering up to 4 transfer s on the transmit and receive side ? general purpose i/o functionality on pins when not used for spi ? queueing operation possible through use of edma
features pxd10 product brief, rev. 1 freescale semiconductor 17 2.4.16 controller area ne twork (can) module the pxd10 contains two can modules that offer the following features: ? compliant with can protocol specification, version 2.0b active ? 64 mailboxes, each configurab le as transmit or receive ? mailboxes configurable while modul e remains synchronized to can bus ? transmit features ? supports configuration of multiple mailboxes to form message queues of scalable depth ? arbitration scheme according to me ssage id or message buffer number ? internal arbitration to guarantee no inner or outer priority inversion ? transmit abort proce dure and notification ? receive features ? individual programmable filters for each mailbox ? 8 mailboxes configurable as a 6-entry receive fifo ? 8 programmable acceptance filters for receive fifo ? programmable clock source ? system clock ? direct oscillator clock to avoid pll jitter ? listen only mode capabilities ?can sampler ? can catch the first message sent on the can network while the pxd10 is stopped. this guarantees a clean startup of the system without missing message s on the can network. ? the can sampler is connected to one of the can rx pins. 2.4.17 inter-ic communications (i 2 c) module the i 2 c module features the following: ? up to four i 2 c modules supported ? two-wire bi-directional serial bus for on-board communications ? compatibility with i 2 c bus standard ? multimaster operation ? software-programmable for one of 256 different serial clock frequencies ? software-selectable acknowledge bit ? interrupt-driven, byte-by-byte data transfer ? arbitration-lost interrupt with automati c mode switching from master to slave ? calling address iden tification interrupt ? start and stop signal generation/detection ? repeated start signal generation ? acknowledge bit generation/detection
pxd10 product brief, rev. 1 features freescale semiconductor 18 ? bus-busy detection 2.4.18 real time counter (rtc) the real timer counter supports wake-up from lo w power modes or real time clock generation ? configurable resolution for different timeout periods ? 1 s resolution for >1 hour period ? 1 ms resolution for 2 second period ? selectable clock sources from external 32 khz crystal, extern al 4?16 mhz crystal, internal 128 khz rc oscillator or divide d internal 16 mhz rc oscillator 2.4.19 enhanced modular input/ output system (timers, pwm) pxd10 microcontrollers have two emios modules ?one with 16 channels and one with 8?with input/output channels supporting a range of 16-bit input capture, out put compare, and pulse width modulation functions. the modules are configurable and can implement 8-channel, 16-bit input capture/output compare or 16-channel, 16-bit output pulse widt h modulation/input compare/output co mpare. up to five additional channels are configurab le as modulus counters. emios features include: ? selectable clock source from main fmpll, a uxiliary fmpll, external 4?16 mhz oscillator or 16 mhz internal rc oscillator ? timed i/o channels with 16-bit counter resolution ? buffered updates ? support for shifted pwm outputs to mini mize occurrence of concurrent edges ? edge aligned output pulse width modulation ? programmable pulse pe riod and duty cycle ? supports 0% and 100% duty cycle ? shared or independent time bases ? programmable phase sh ift between channels ? selectable combination of pairs of emios outputs to support sound generation ? dma transfer support ? selectable clock source from the primary fmpll, auxiliar y fmpll, external 4?16 mhz oscillator or the 16 mhz internal rc oscillator. the channel configuration options for the 16-channel emios module are summarized in table 3 .
features pxd10 product brief, rev. 1 freescale semiconductor 19 the channel configuration options for the 8-channel emios module are summarized in table 4 . 2.4.20 periodic interrupt timer (pit) module the pit features the following: ? four general purpos e interrupt timers ? up to 2 dedicated interrupt time rs for triggering adc conversions ? 32-bit counter resolution ? clocked by system clock frequency ? 32-bit counter for real time interrupt, clocked from main external oscillator table 3. 16-channel emios module channel configuration channel mode channel number 8 ic/oc counter 9?15 ic/oc 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output xxxxx single action input capture xxxxx single action output compare xxxxx modulus counter buffered 1 notes: 1 modulus up and down counters to support driving local and global counter busses xxx output pulse width and frequency modulation buffered xxx output pulse width modulation buffered x x x table 4. 8-channel emios module channel configuration channel mode channel number 16 pwm counter 17?22 pwm 23 pwm counter general purpose input/output x x x single action input capture x x x single action output compare x x x modulus counter buffered 1 notes: 1 modulus up and down counters to support driving local and global counter busses xx output pulse width and frequency modulation buffered xxx output pulse width modulation buffered x x x
pxd10 product brief, rev. 1 features freescale semiconductor 20 2.4.21 system timer module (stm) the stm is a 32-bit timer designed to support commonly required system and application software timing functions. the stm includes a 32-bit up counter and four 32-bit compare channels with a separate interrupt source for each channel. the counter is driven by the system clock divided by an 8-bit prescale value (1 to 256). ? one 32-bit up counter with 8-bit prescaler ? four 32-bit compare channels ? independent interrupt source for each channel ? counter can be stopped in debug mode 2.4.22 software watchdog timer (swt) the swt features the following: ? watchdog supporting software acti vation or enabled out of reset ? supports normal or windowed mode ? watchdog timer value wr itable once after reset ? watchdog supports optional ha lting during low power modes ? configurable response on timeout: reset, in terrupt, or interrupt followed by reset ? selectable clock source for main system cl ock or internal 16 mhz rc oscillator clock 2.4.23 interrupt controller (intc) the intc provides priority-based preemptive scheduli ng of interrupt requests, suitable for statically scheduled hard real-time systems. for high priority interrupt requests, the time from the assertion of the interrupt request from the peripheral to when the processor is executi ng the interrupt service routine (i sr) has been minimized. the intc provides a unique vector for each inte rrupt request source for quick dete rmination of which isr needs to be executed. it also provides an ample number of prior ities so that lower priority isrs do not delay the execution of higher priority isrs. to allow the appropria te priorities for each s ource of interrupt request, the priority of each interrupt re quest is software configurable. when multiple tasks share a resour ce, coherent accesses to that resource need to be supported. the intc supports the priority ceiling protocol for coherent accesses. by providi ng a modifiable priority mask, the priority can be raised temporarily so that all tasks which share the resource can not preempt each other. multiple processors can assert interru pt requests to each other through soft ware settable interrupt requests. these same software settable interr upt requests also can be used to break the work involved in servicing an interrupt request into a high pr iority portion and a low priority portion. the high priority portion is initiated by a peripheral interrupt request, but then the isr asserts a software settable interrupt request to finish the servicing in a lower priority isr. therefore these software settable inte rrupt requests can be used instead of the peripheral isr scheduling a task through the rtos. the intc provides the following features:
features pxd10 product brief, rev. 1 freescale semiconductor 21 ? unique 9-bit vector for each of the po ssible 128 separate interrupt sources ? eight software-triggerable interrupt sources ? 16 priority levels with fixed hardware arbitrati on within priority levels for each interrupt source ? ability to modify the isr or task priority. ? modifying the priority can be used to implem ent the priority ceiling protocol for accessing shared resources. ? external non-maskable in terrupt directly accessing the main core cri tical interrupt mechanism ? 32 external interrupts 2.4.24 system integration unit (siu) the siu controls mcu reset confi guration, pad configuration, external interrupt, general purpose i/o (gpio), internal peripheral multiple xing, and the system reset operation. the gpio features the following: ? up to 4 levels of internal pin multiplexing, allo wing exceptional flexibility in the allocation of device functions for each package ? centralized general purpose input output (gpio) control of up to 132 input/output pins (package dependent) ? all gpio pins can be independently conf igured to support pul l-up, pull down, or no pull ? reading and writing to gpio supported both as individual pins and 16-bit wide ports ? all peripheral pins can be alte rnatively configured as both gene ral purpose input or output pins except adc channels which support alternative configurat ion as general purpose inputs ? direct readback of the pin value supported on all digita l output pins through the siu ? configurable digital input filter that can be appl ied to up to 14 general pur pose input pins for noise elimination on external interrupts ? register configuration protected ag ainst change with soft lock for temporary guard or hard lock to prevent modification until next reset. 2.4.25 system clocks and clock generation modules the system clock on the pxd10 can be derived from an external oscillator, an on-chip fmpll, or the internal 16 mhz oscillator. ? the source system clock freque ncy can be changed via an on-ch ip programmable clock divider ( ? 1 to ?? 2). ? additional programmabl e peripheral bus cl ock divider ratio ( ? 1 to ? 16) ? the pxd10 has 2 on-chip fmplls?the pr imary module and an auxiliary module. ? each features the following: ? input clock frequency from 4 mhz to 16 mhz ? lock detect circuitry conti nuously monitors lock status ? loss of clock (loc) detection fo r reference and feedback clocks
pxd10 product brief, rev. 1 features freescale semiconductor 22 ? on-chip loop filter (for impr oved electromagnetic interfer ence performance and reduction of number of external components required) ? support for frequency ramping from pll ? the primary fmpll module is for use as a system clock s ource. the auxiliary fmpll is available for use as an altern ate, modulated or non-modulated clock source to emios modules and as alternate clock to the dcu for pixel clock generation. ? the main oscillator provides the following features: ? input frequency range 4?16 mhz ? square-wave input mode ? oscillator input mode 3.3 v (5.0 v) ? automatic level control ? pll reference ? pxd10 includes a 32 khz low power external oscillator for slow execution, low power, and real time clock ? dedicated internal 128 khz rc oscillator fo r low power mode operation and self wake-up ? 10% accuracy across vol tage and temperature (a fter factory trimming) ? trimming registers to suppor t improved accuracy with in-application calibration ? dedicated 16 mhz inte rnal rc oscillator ? used as default clock source out of reset ? provides a clock for rapid st art-up from low power modes ? provides a back-up clock in the event of pll or external oscillator clock failure ? offers an independent clock source for the watchdog timer ? 5% accuracy across voltage and te mperature (after factory trimming) ? trimming registers to support frequency ad justment with in-appl ication calibration 2.4.26 crossbar switch (xbar) the xbar multi-port crossbar switch supports simultaneous connections between four master ports and four slave ports. the crossbar supports a 32-bi t address bus width and a 32-bit data bus width. the crossbar allows four concurrent transactions to occur from any ma ster port to any slave port but one of those transfers must be an inst ruction fetch from internal flash. if a slave port is simultaneously requested by more than one master por t, arbitration logic selects the highe r priority master and grants it ownership of the slave port. all other masters requesting that slave port are stalled until the higher priority master completes its transactions. requesting masters having equal priori ty are granted access to a slave port in round-robin fashion, based upon the id of the last master to be granted access. the crossbar provides the following features: ? 4 master ports ? e200z0h core instruction port ? e200z0h core complex load/store data port ? edma controller
features pxd10 product brief, rev. 1 freescale semiconductor 23 ? display control unit ? 4 slave ports ? 1 flash port dedicated to the cpu ? platform sram ? quadspi serial flash controller ? 1 slave port combining: ? flash port dedicated to the disp lay control unit and edma module ? graphics sram ? peripheral bridge ? 32-bit internal address bus , 32-bit internal data bus 2.4.27 enhanced direct memory access (edma) the edma module is a controller capable of performing complex da ta movements via 16 programmable channels, with minimal intervention from the host processor. the hardware micro architecture includes a dma engine which performs source and destination address calculations , and the actual data movement operations, along with an sram-based memory containing the transfer control descriptors (tcd) for the channels. this implementation is utilized to minimize the overall bl ock size. the edma module provides the following features: ? 16 channels support independent 8-, 16- or 32-bit single value or block transfers ? supports variable sized que ues and circular queues ? source and destination address regi sters are independently configured to post-increment or remain constant ? each transfer is initiated by a peripheral, cpu, periodic timer interrupt or edma channel request ? each dma channel can optionally send an interrupt request to th e cpu on completion of a single value or block transfer ? dma transfers possible between sy stem memories, quadspi, spis, i 2 c, adc, emios and general purpose i/os (gpios) ? programmable dma channel mux allows assignm ent of any dma source to any available dma channel with up to a total of 64 potential request sources. 2.4.28 memory protection unit (mpu) the mpu features the following: ? 12 region descriptors for per-master protection ? start and end address defi ned with 32-byte granularity ? overlapping regions supported ? protection attributes can optionally include process id ? protection offered for 3 concurrent read ports ? read and write attri butes for all masters ? execute and supervisor/user mode attributes for processor masters
pxd10 product brief, rev. 1 features freescale semiconductor 24 2.4.29 boot assist module (bam) the bam is a block of read-only memory that is programmed once by freescale. the bam program is executed every time the mcu is powered-on or reset in normal mode. the bam s upports different modes of booting. they are: ? booting from internal flash memory ? serial boot loading (a program is downloaded into ram via can or uart and then executed) ? booting from external memory additionally, the bam: ? enables and manages the transition of the mcu from reset to user code execution ? configures device for serial bootload ? enables multiple bootcode starting locations out of reset through implem entation of search for valid reset configuration halfword ? enables or disables software watchdog timer out of reset through ba m read of the reset configuration halfword option bit 2.4.30 ieee 1149.1 jtag controller (jtagc) jtagc features the following: ? backward compatible to standard jtag ie ee 1149.1-2001 test access port (tap) interface ? support for boundary scan testing 2.4.31 nexus development interface (ndi) nexus features the following: ? per ieee-isto 5001-2003 ? nexus 2 plus features supported ? static debug ? watchpoint messaging ? ownership trace messaging ? program trace messaging ? real time read/write of any internally memory mapped resources through jtag pins ? overrun control, which selects whether to stal l before nexus overruns or keep executing and allow overwrite of information ? watchpoint triggering, watchpoint triggers program tracing ? configured via the ieee 1149.1 (jtag) port ? nexus auxiliary port supported on the 176 lqfp package for development only ? narrow auxiliary nexus port suppor ting support trace, with 2 mdo pins ? wide auxiliary nexus port supporting highe r bandwidth trace, with 4 mdo pins
developer support pxd10 product brief, rev. 1 freescale semiconductor 25 3 developer support this family of mcus is supported by freescale?s towe r development system as well as a broad set of advanced debug and runtime software: ? codewarrior ?freemaster ?mqx ? rappid init ? rappid toolbox ? swell peg/peg+/peg pro 4 orderable parts figure 2. pxd10 orderable part number description table 5. pxd10 orderable part number summary part number flash/sram package speed (mhz) mPXD1005vlq64 512 kb / 48 kb 144 lqfp (20 mm x 20 mm) 64 mpxd1010vlq64 1 mb / 48 kb 144 lqfp (20 mm x 20 mm) 64 mpxd1010vlu64 1 mb / 48 kb 176 lqfp (24 mm x 24 mm) 64 mpx 10 note: not all options are available on all devices. see ta bl e 5 for more information. d qualification status brand family class flash memory size temperature range v = ?40 c to 105 c operating frequency 64 = 64 mhz tape and reel status r = tape and reel (blank) = trays qualification status p = pre-qualification (engineering samples) m = fully spec. qualified, general market flow s = fully spec. qualified, automotive flow 10 v temperature range lu package identifier 64 r operating frequency tape and reel indicator package identifier lq = 144 lqfp 120 = 120 mhz (ambient) lu = 176 lqfp family d = display graphics n = connectivity/network r = performance/real time control s=safety flash memory size 05 = 512 kb 10 = 1 mb
document number: pxd10pb rev. 1 06/2011 how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor china ltd. exchange building 23f no. 118 jianguo road chaoyang district beijing 100022 china +86 10 5879 8000 support.asia@freescale.com freescale semiconductor literature distribution center 1-800-441-2447 or +1-303-675-2140 fax: +1-303-675-2150 ldcforfreescalesemiconduc tor@hibbertgroup.com information in this document is provid ed solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability arising out of the application or use of any product or circuit, and specif ically disclaims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale semiconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applic ations intended to support or sustain life, or for any other application in which the failure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemnify and hold freescale semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics as thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http://www.freescale.com/epp . freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc. 2011. all rights reserved. 5 revision history table 6 summarizes revisions to this document. table 6. revision history revision (date) description rev. 1 june 2011 initial release.

▲Up To Search▲

Price & Availability of PXD1005

	To Download PXD1005 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .